Electronic News: Without PGS, UDSM Tapeout Is Like Playing "Russian Roulette"

With the rapid adoption of 0.25- and 0.18-micron semiconductor process technologies (also called ultra deep submicron [UDSM]), a new form of physical verification has emerged to complement design rule checking (DRC) and layout vs. schematic checking (LVS). In 1999, the tall, thin wires and lower voltages of these UDSM technologies reduce the margin for error in power grid design. A voltage or IR drop of more than 10 percent on the power grid can produce a 30 percent reduction in the performance of an IC. Even worse, IR drop can cause an IC design to fail at the prototype phase or later when installed in the customers' products. The new physical verification step to find these failures is called Power Grid Sign-Off (PGS).

Foundries such as IBM, TSMC and UMC Group are embracing PGS as a way to reduce design re-spins and improve their ramp to revenue. It's not happening just in the fabless, pure-play model either. For example, ASIC design teams at companies like Sun Microsystems are making PGS a requirement of their ASIC vendors.

Why is this? The most prevalent physical failure undetected by any previously existing tool is IR drop on the power grid. Based on a recent sample of over 50 designs, one out of five designs would have failed without PGS, and 75 percent were modified for better performance and/or reliability due to the results from performing PGS.

Companies all over the world are experiencing silicon spins caused by IR drops on the power grid. For example, one company found potentially fatal problems in their power grid as they migrated from 0.35 micron to 0.25-micron. Their existing physical verification tools (DRC and LVS) told them nothing about these problems. Another design team experienced unexpected IR drop because of an unconnected route on the power grid.

The good news is that these companies are finding their power grid problems through the use of PGS before it's too late. PGS does what DRC and LVS did for IC designers in the early 1980s. As design rules become more complex while design sizes increase, new verification steps are needed to prevent catastrophic failures that would be too difficult or impossible to find manually. Now, the dominance of interconnect has changed all stages of the design flow including physical verification.

Because IR drop is a full-chip issue triggered by the flow of current across the chip, PGS tools must be robust enough to handle millions of transistors and fast enough to be used as a sign-off procedure on every design. To perform PGS, the design team first runs a full-chip static IR drop analysis. This quick first- pass analysis can be performed in a matter of hours. It gives the design team a good overall view of their design's power distribution and enables them to identify any "hot spots". Then, the design team can use simulation vectors to run more detailed, dynamic analysis on the identified hot spots.

PGS is being adopted in both the fabless and ASIC market segments. In the pure- play foundry model, foundries rely on fabless design teams to verify the functionality and performance of their designs before "tapeout". When a fabless design fails on first silicon, it creates a serious business problem for both partners. Design "re-spins" reduce the window of market opportunity for the fabless company and postpone volume production for the foundry. The result is reduced lifetime revenue and profit for both.

What design team has the luxury to play "Russian roulette" with their tapeout? In order to have tapeout confidence at 0.25 micron and below, IC designers must add PGS to their physical verification procedures. The tools they choose must satisfy the requirements of a fast, full-chip methodology and be supported by their foundries of choice.

Penny Herscher is president and chief executive officer of Simplex Solutions Inc., based in Sunnyvale, Calif.